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DISCRETE SEMICONDUCTORS
DATA SHEET
BF998WR N-channel dual-gate MOS-FET
Product specification Supersedes data of 1995 Apr 25 File under Discrete Semiconductors, SC07 1997 Sep 05
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
FEATURES * High forward transfer admittance * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier up to 1 GHz. APPLICATIONS * VHF and UHF applications with 12 V supply voltage, such as television tuners and professional communications equipment. DESCRIPTION Depletion type field-effect transistor in a plastic microminiature SOT343R package with source and substrate interconnected. The transistor is protected against excessive input voltage surges by integrated back-to-back diodes between gates and source. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling.
Marking code: MB.
BF998WR
PINNING PIN 1 2 3 4 SYMBOL s, b d g2 g1 source drain gate 2 gate 1 DESCRIPTION
d
3 4
g2 g1
2
1
s,b
Top view
MAM198
Fig.1 Simplified outline (SOT343R) and symbol.
QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj yfs Cig1-s Crs F drain current total power dissipation operating junction temperature forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure f = 1 MHz f = 800 MHz PARAMETER drain-source voltage CONDITIONS - - - - - - - - MIN. - - - - 24 2.1 25 1 TYP. MAX. 12 30 300 150 - - - - UNIT V mA mW C mS pF fF dB
1997 Sep 05
2
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Device mounted on a printed-circuit board. PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature up to Tamb = 45 C; see Fig.2; note 1 CONDITIONS - - - - - -65 - MIN.
BF998WR
MAX. 12 30 10 10 300 +150 +150 V
UNIT mA mA mA mW C C
MLD154
handbook, halfpage
400
Ptot (mW) 300
200
100
0 0 50 100 150 200 Tamb ( oC)
Fig.2 Power derating curve.
1997 Sep 05
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-s Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL V(BR)G1-SS V(BR)G2-SS V(P)G1-S V(P)G2-S IDSS IG1-SS IG2-SS PARAMETER gate 1-source breakdown voltage gate 2-source breakdown voltage gate 1-source cut-off voltage gate 2-source cut-off voltage drain-source current gate 1 cut-off current gate 2 cut-off current CONDITIONS VG2-S = VDS = 0; IG1-S = 10 mA VG1-S = VDS = 0; IG2-S = 10 mA VG2-S = 4 V; VDS = 8 V; ID = 20 A VG1-S = 0; VDS = 8 V; ID = 20 A VG2-S = 4 V; VDS = 8 V; VG1-S = 0 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 5 V MIN. 6 6 - - 2 - - PARAMETER thermal resistance from junction to ambient thermal resistance from junction to soldering point CONDITIONS note 1 note 2; Ts = 90 C
BF998WR
VALUE 350 200
UNIT K/W K/W
MAX. 20 20 -2.5 -2 18 50 50
UNIT V V V V mA nA nA
DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; ID = 10 mA; VDS = 8 V; unless otherwise specified. SYMBOL yfs Cig1-s Cig2-s Cos Crs F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 drain-source capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BSopt CONDITIONS pulsed; Tj = 25 C MIN. 22 - - - - - TYP. 25 2.1 1.2 1.05 25 0.6 1 MAX. - 2.5 - - - - - UNIT mS pF pF pF fF dB dB
reverse transfer capacitance f = 1 MHz
f = 800 MHz; GS = 3.3 mS; BS = BSopt -
1997 Sep 05
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
MGC471
MGC470
24 3V ID (mA) 16 V G2 S = 4 V 2V
24 ID (mA) 0.3 V 1V 16 0.2 V 0.1 V 0V V G1 S = 0.4 V
8
8
-0.1 V -0.2 V
0V 0 1 0 V G1 S (V) 1 0 0 2 4 6 8
-0.3 V -0.4 V -0.5 V 10 V DS (V)
VDS = 8 V. Tamb = 25 C.
VG2-S = 4 V. Tamb = 25 C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MGC472
MGC473
24 y fs ID (mS) 16 max typ
30 (mS) 24
4V
3V 2V 1V 18
min 8
12
6 V G2 - S = 0 V 0 -1600 -1200 -800 -400 0 0 400 VG1 (mV) 0 4 8 12 16
0.5 V
20 I D (mA)
VDS = 8 V; VG2 = 4 V; Tamb = 25 C.
VDS = 8 V; Tamb = 25 C.
Fig.5
Drain current as a function of gate 1 voltage; typical values.
Fig.6
Forward transfer admittance as a function of drain current; typical values.
1997 Sep 05
5
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
MGC474
MGC475
30 y fs (mS) 24 V G2 S = 4 V
1.5 Cos (pF) 1.4
3V 18 1.3
12
2V
1.2
ID = 12 mA
6
1V
1.1
10 mA 8 mA
0V 0 -1 1.0 0 VG1-S (V) 1 4 6 8 10 12 14 VDS(V)
VDS = 8 V; Tamb = 25 C.
VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.
Fig.7
Forward transfer admittance as a function of gate 1 voltage; typical values.
Fig.8
Output capacitance as a function of drain-source voltage; typical values.
MGC476
MGC477
2.4 Cis (pF) 2.2
2.4 Cis (pF) 2.3
2.0 2.2 1.8 2.1 1.6
1.4 -2.4
-1.6
-0.8
2.0 0 0.8 VG1-S (mV) 6 4 2 0 VG2-S (V)
-2
VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.
VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 C.
Fig.9
Gate 1 input capacitance as a function of gate 1-source voltage; typical values.
Fig.10 Gate 1 input capacitance as a function of gate 2-source voltage; typical values.
1997 Sep 05
6
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
MGC466
10 y is (mS) b is 1
10 3 y rs (S) 10 2
MGC467
10 3
rs (deg)
rs
y rs
10 2
10 1 g is
10
10
10 2 10
102
f (MHz)
10 3
1 10
1 102 f (MHz) 10 3
VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C.
VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C.
Fig.11 Input admittance as a function of the frequency; typical values.
Fig.12 Reverse transfer admittance and phase as a function of frequency; typical values.
10 2
MGC468
10 2
MGC469
10 yos (mS) 1
y fs (mS)
y fs
fs
(deg)
bos
10
10 fs 10 1 gos
1 10
1 102 f (MHz) 10 3
10 2 10
102
f (MHz)
10 3
VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C.
VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C.
Fig.13 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.14 Output admittance as a function of the frequency; typical values.
1997 Sep 05
7
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
VDD
47 F 1 nF VAGC 1 nF 1.8 k 1 nF 1 nF L2 50 input 20 H
47 k 1 nF C1 5.5 pF 50 input L1 140 k VDD 1 nF D1 BB405 100 k 1 nF V tun input 330 k 15 pF
1 nF 360
10 pF
D2 BB405
330 k
1 nF V tun output
MGC481
VDD = 12 V; GS = 2 mS; GL = 0.5 mS. L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm. L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm. Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS.
Fig.15 Gain control testcircuit at f = 200 MHz.
1997 Sep 05
8
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF998WR
V DD 140 k
VAGC 1 nF
VDD
1 nF 270 k L3 L4 1 nF
100 k
1 nF
50 input
L1 1 nF L2
1 nF 1 nF
C3 0.5-3.5 pF
C4 4-40 pF
50 input
MGC480
C1 2-18 pF
C2 0.5-3.5 pF
1.8 k
360
V DD VDD = 12 V; GS = 3.3 mS; GL = 1 mS. L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm. L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane. L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
Fig.16 Gain control test circuit at f = 800 MHz.
MGC479
MGC478
Gtr (dB)
0
Gtr (dB)
0
-10
-10 IDSS= max typ min
-20
-20
-30
-30
-40
-50
IDSS= max typ min 0 2 4 6 10 8 VAGC(V)
-40
-50
0
2
4
6
8 10 VAGC(V)
VDD = 12 V; f = 200 MHz; Tamb = 25 C.
VDD = 12 V; f = 800 MHz; Tamb = 25 C.
Fig.17 Automatic gain control characteristics measured in circuit of Fig.15.
Fig.18 Automatic gain control characteristics measured in circuit of Fig.16.
1997 Sep 05
9
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
PACKAGE OUTLINE
BF998WR
handbook, full pagewidth
1.00 max 0.2 M A 0.2 M B 0.4 0.2 0.1 max 0.2 A
3
4
2.2 2.0
1.35 1.15
2
1
0.7 0.5 1.4 1.2 2.2 1.8 B
0.3 0.1 0.25 0.10
MSB367
Dimensions in mm.
Fig.19 SOT343R.
1997 Sep 05
10
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values
BF998WR
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Sep 05
11
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
117067/00/02/pp12
Date of release: 1997 Sep 05
Document order number:
9397 750 02671

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